1. Field of the Invention
The current invention generally relates to electronic systems having a plurality of clocks, the clocks having related frequencies. More particularly, the current invention detects if each of the plurality of clocks is operating at a proper speed relative to other clocks in the plurality of clocks, and has phase and jitter characteristics are within predetermined bounds.
2. Description of the Related Art
Electronic systems, such as, for examples, computer systems or components of computer systems, often have a plurality clocks having required relationships between different clocks in the plurality of clocks. For example, an electronic system may have two clocks that must have the same frequency. As another example, the electronic system may have a first clock having a first frequency, and a second clock having a second frequency that is a multiple of the first frequency. For example, in electronic systems having a phase locked loop (PLL), a designer must detect when the PLL has locked onto an oscillator frequency coupled to the PLL.
For example, if two clocks are required to have the same frequency, the designer may have additional requirements as to phase relationships between the two clocks, and may have further requirements as to jitter between the two clocks. The phase and jitter relationships between the two clocks need to be margin tested during system test. Jitter is temporary frequency changes in the first clock relative to the second clock. During system test, stress testing of the phase and jitter relationships should be performed. During normal operation of the electronic system, the frequency, phase, and jitter requirements must be guaranteed. During testing of a prototype electronic system, relaxed tolerance of frequency, phase, and jitter are often allowable, and a programmable test of such relationships is desired.
Existing art, such as U.S. Pat. No. 6,418,502, “AGP Clock Start/Stop Detection Circuit”, for example, provide detection that two clocks (i.e., AGP_CLK and STROBE clock) have a proper frequency relationship. However, the existing art does not provide a programmable method and apparatus to provide accommodation for, or stress testing of, phase and jitter relationships between clocks in a plurality of clocks in an electronic system.
Therefore, there is a need for a method and apparatus to provide programmable accommodation for stress testing of phase and jitter relationships between clocks in a plurality of clocks in an electronic system.